Technological advances in semiconductor integrated circuit (IC) materials, design, processing, and manufacturing have enabled scaling IC devices where each generation has smaller and more complex circuits than the previous generation.
Processes for fabricating wafers of integrated circuits consist of a series of steps by which a set of geometric patterns, determined by the transistors and their interconnections, are transformed onto numerous superimposed layers made of semiconductor, insulating, and conducting materials on top of a substrate. The interconnection of superimposed layers is achieved by connecting conductive lines in the layers with conductive contact holes and vias, the contact holes and vias being processed like plugs perpendicular to the layers where the conductive lines reside. However, as transistors are scaled down to form integrated circuits with higher levels of integration and faster speeds, physical phenomena from tight pitch P of circuits impinge the desired performance of the interconnecting circuitry. In the case of a conductive layer, metal lines ideally should remain at designed widths. However, metal linewidth varies from many factors. For example, some lines shrink or swell because of the optical proximity effect in the lithographic process, and other lines change from surface topography differences in regions with different pattern densities, for example, as a result of uneven loads in a chemical mechanical polishing (CMP) process or an etching process. The optical proximity effect during lithography process generates a linewidth bias between isolated and dense features. Process limitations degrade effective critical dimensions on the wafer. In some cases, an isolated line can be printed much wider than dense lines of the same designed width. The linewidth bias induces the film stress at the dense-to-isolated line transition vicinity (also called the line estuaries), generating defects known as metal pits, for example, the “copper line voids”. In an extreme case, metal lines may “lift off” or simply break. Although IC manufacturers have implemented various strategies including Optical Proximity Correction (OPC) models and sophisticated design rules in circuitry layout to better control critical dimensions, it has been a challenging task to avoid metal line stress defects at the metal line estuaries. Although described as a metal line problem, the line estuary stress also resides in processing lines of poly, dielectric, semiconductors, and other materials.
Therefore, an effective and easy-to-implement technique is desired to reduce line stress at the dense-to-isolated line transitional area in IC process and manufacturing.